Cache Memory & Multicore Processors Essay

The computer that might be considered for purchasing has Intel Core i5-6600 CPU. This CPU is not the most advanced one, but it has a decent balance of performance and price. This CPU has three levels of cache memory: it has 4 x 32 KB instruction cache and 4 x 32 KB data cache at L1 level, total 4 x 256 KB L2 cache and 6MB L3 cache (Intel Smart Cache) (Intel, 2016). While L1 and L2 cache levels are specific for each of four cores, L3 cache is shared, since Intel Smart Cache technology allows to share the last L3 cache level between all cores. L1 and L2 cache memory interacts with their “own” cores in this CPU, while a circular bus is used to connect L3 cache with all cores, memory controller, graphic and calculation systems and system agent (Intel, 2016).

In general, L1 cache is the smallest but the most efficient in terms of retrieving information. It is typically used to store instructions and some of the most frequently used data portions. L2 cache is larger and therefore is slightly slower; L3 cache represents the third layer of caching that introduces even more latency, but is significantly greater compared to L2. With regard to efficiency, in terms of time L1 is most efficient, then goes L2 and L3 is the least efficient as it takes longer to retrieve data from L3 (however, this process is still faster than retrieving information from the RAM). With regard to volume of data stored, the order is reverse: L3, then L2, and then L1. L1 cache gives significant advantages while performing a lot of instructions such as calculations, while L2 and L3 caches are efficient when there are groups of frequently reused portions of data or instructions (Roosta, 2012).

Two approaches to organizing multiprocessing systems are master-slave and symmetric. The advantages of master-slave approach are: high processing speed when CPU-bound processes are required and easier approach to configuring multiprocessing (as master controls slave processors) (Roosta, 2012). However, this approach is weak when many input-output operations (controlled by the master) have to be performed simultaneously (thus creating a bottleneck). Thus, this approach is also more vulnerable to overheating. Symmetric approach is significantly more complex in terms of organization and configuration, but it allows to create a more flexible and more robust system. Such system would be less prone to overheating, because the role of “master” floats between processors (Roosta, 2012). Processing speed in this case would be higher for complex tasks requiring involving various resources. For such tasks as Word processing and Excel spreadsheets, a master-slave system is sufficient, since the workload is relatively static, and there is a limited number of I/O operations. However, for computer gaming symmetric approach is more suitable, as it can handle the great number of user actions and complex calculations at the same time.

References

Intel. (2016). Intel Core i5-6600 Processor. Intel. Retrieved from http://ark.intel.com/products/88188/Intel-Core-i5-6600-Processor-6M-Cache-up-to-3_90-GHz

Roosta, S.H. (2012). Parallel Processing and Parallel Algorithms: Theory and Computation. Springer Science & Business Media.

The terms offer and acceptance. (2016, May 17). Retrieved from

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"The terms offer and acceptance." freeessays.club, 17 May 2016.

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freeessays.club (2016) The terms offer and acceptance [Online].
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[Accessed: February 4, 2023]

"The terms offer and acceptance." freeessays.club, 17 May 2016

[Accessed: February 4, 2023]

"The terms offer and acceptance." freeessays.club, 17 May 2016

[Accessed: February 4, 2023]

"The terms offer and acceptance." freeessays.club, 17 May 2016

[Accessed: February 4, 2023]

"The terms offer and acceptance." freeessays.club, 17 May 2016

[Accessed: February 4, 2023]
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